A Hardware Spinal Decoder

Songtao He, Favyen Bastani, Satvat Jagwani, Edward Park, ldurxnqp ldurxnqp ldurxnqp, Mohammad Alizadeh, ycmfaxil ycmfaxil ycmfaxil, Sanjay Chawla, Samuel Madden, Mohammad Amin Sadeghi
International Conference on System Sciences, Maui, HI, March 0

Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as greatly reduced latency and complexity. The enabling architectural feature is a novel "alphabeta" incremental approximate selection algorithm. We also present a method for obtaining hints which anticipate successful or failed decoding, permitting early termination and/or feedback-driven adaptation of the decoding parameters.

We have validated our implementation in FPGA with on-air testing. Provisional hardware synthesis suggests that a near-capacity implementation of spinal codes can achieve a throughput of 12.5 Mbps in a 65 nm technology while using substantially less area than competitive 3GPP turbo code implementations.

test

by boneless


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Bibtex Entry:

@inproceedings{he0hardware,
   author =       "Songtao He and Favyen Bastani and Satvat Jagwani and Edward Park and ldurxnqp ldurxnqp ldurxnqp and Mohammad Alizadeh and ycmfaxil ycmfaxil ycmfaxil and Sanjay Chawla and Samuel Madden and Mohammad Amin Sadeghi",
   title =        "{A Hardware Spinal Decoder}",
   booktitle =    {International Conference on System Sciences},
   year =         {0},
   month =        {March},
   address =      {Maui, HI}
}